ASIC Digital Design, Principal Engineer

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

You have spent a decade or more designing digital logic that has to work at the edge of what silicon can do. High-speed SerDes, clock domain crossings that could sink a tapeout, power budgets measured in milliwatts because every one counts. You know that the hardest part of mixed-signal ASIC design is not the RTL, it is the boundary between digital and analog, where timing meets noise and specifications meet reality.

Responsibilities

• Architect and design digital subsystems for high-speed SerDes IP including Backplane Ethernet, PCIe, SATA, and USB 2/3 PHYs
• Analyze and define digital and analog interface specifications, translating system-level requirements into implementable RTL and design constraints
• Drive design flow decisions for clock domain crossing, synthesis, DFT insertion, and low-power architecture across complex mixed-signal blocks
• Collaborate directly with ASIC verification engineers to define testplans, review assertion and code coverage, and close functional coverage gaps
• Perform gate-level simulation, analyze timing and power, and debug failure cases across digital and mixed-signal boundaries
• Mentor junior design engineers on RTL quality, design intent, synthesis impact, and cross-functional collaboration
• Work across design groups and customer support teams to resolve design issues, clarify specifications, and support silicon bring-up

The Impact You Will Have

• Your architectural decisions will define the performance, power, and area of SerDes IP used in high-volume networking and storage products worldwide
• The design flows and methodologies you establish will set the standard for how the team handles CDC, DFT, and low-power design across future product generations
• Your collaboration with verification will reduce tapeout risk and catch critical issues before they reach silicon
• The testplans and coverage strategies you help create will directly improve functional quality and reduce post-silicon debug cycles
• Your mentorship will accelerate the growth of junior engineers and raise the technical bar across the team
• The specifications you write will become the foundation for cross-functional alignment between digital, analog, verification, and implementation teams
• Your work will enable customers to deliver faster, lower-power, more reliable connectivity in everything from data centers to consumer devices

Requirements

• Master's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience
• 10+ years of hands-on digital ASIC design experience, with significant work in high-speed or mixed-signal environments
• Strong proficiency in Verilog or VHDL for RTL design and gate-level simulation
• Deep understanding of clock domain crossing design, analysis, and verification methodologies
• Hands-on experience with synthesis tools and techniques, including timing closure and power optimization
• Solid knowledge of DFT methodologies including scan insertion, ATPG, and boundary scan
• Experience working closely with verification teams on testplan creation, coverage closure, and failure analysis. Familiarity with high-speed digital interfaces such as Ethernet, PCIe, SATA, or USB is a strong plus.

Benefits

• Comprehensive medical and healthcare plans that work for you and your family
• In addition to company holidays, we have ETO and FTO Programs
• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
• Purchase Synopsys common stock at a 15% discount, with a 24-month look-back
• Save for your future with our retirement plans that vary by region and country
• Competitive salaries