Description
The Silicon One team at Cisco creates innovative hardware platforms central to the AI era, powering core Switching, Routing, and Wireless products for organizations globally.
As a Physical Design Engineer at Silicon One Optics, you will floorplan, tape out, and physically realize next-gen 800G, 1.6T, and multi-terabit optical transceivers and driver ICs.
Key responsibilities:
- Lead end-to-end RTL-to-GDSII physical design implementation across advanced nodes
- Architect and scale digital implementation flows using custom TCL/Python automation
- Lead physical execution across PnR, CTS, MMMC timing closure, and ECO iterations
Requirements:
- Bachelors + 8 years of related experience, or Masters + 6 years of related experience, or PhD + 3 years of related experience
- Prior experience in ASIC/SoC physical design and implementation in advanced tech nodes
- Hands-on experience with EDA tool flows, back-end sign-off criteria, and workflow automation using Python, TCL, and Shell scripts
Preferred qualifications:
- Experience in closing designs with high-speed, high-density, macro-dominant, and I/O cell–intensive blocks
- Experience in STA methodology, SDC timing constraint creation, analysis, and timing ECO generation
- Hands-on experience with functional equivalence checking and functional ECOs
Benefits:
- Medical, dental, and vision insurance
- 401(k) plan with Cisco matching contribution
- Paid parental leave, short and long-term disability coverage, and basic life insurance
- Paid time away, including holidays, vacation time, and sick time
- Opportunities for career growth and professional development