ASIC Digital Design, Principal Engineer

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

As a Principal ASIC Digital Design Engineer and a recognized PCIe technical authority, you will set architecture and write and review RTL. You will define micro-architecture, make trade-offs across performance, power, area, and configurability, and stay in the design until the IP is silicon-proven.

Responsibilities

• Own PCIe digital architecture and RTL for major controller subsystems, from micro-architecture through design convergence and post-silicon support.
• Define micro-architecture, design specifications, and implementation approach for high-performance, low-power, scalable, configurable PCIe IP.
• Make and document key design decisions; act as the go-to authority for protocol, data-path, clocking/reset, and RAS issues.
• Hands-on RTL development: implement critical paths, review detailed design, and drive complex debug (simulation, formal, emulation, and silicon).
• Raise design quality bar through reviews, coding standards, CDC/RDC discipline, and RTL maintainability across a large parameterized codebase.
• Work with verification, formal, emulation, physical design, firmware, and system teams to get IP integrated and silicon-successful.
• Influence PCIe IP technical strategy, roadmap, and next-generation architecture, including CXL and automotive variants.
• Communicate status, technical risk, and trade-offs to senior management, architects, and customers.

Requirements

• BSEE with 12+ years of relevant experience, or MSEE with 10+ years.
• Demonstrated Principal / Staff-plus technical leadership in ASIC digital design.
• Direct RTL ownership of complex, production digital designs.
• Deep PCIe controller/core digital design and architecture experience, CXL, AMBA, DDR, UCIe, or similar protocols strongly desired.
• Proven ability to define micro-architecture and take designs from concept through silicon.
• Strong ASIC fundamentals: multi-clock design, CDC/RDC, resets, low power, DFT, synthesizable RTL, and timing-aware design.
• Experience with highly configurable / parameterized IP is strongly desired.
• Scripting for design automation (Python, TCL, Perl) is desirable. Familiarity with AI-assisted design tools and flows is a plus.

Benefits

• Comprehensive medical and healthcare plans that work for you and your family.
• In addition to company holidays, we have ETO and FTO Programs.
• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
• Purchase Synopsys common stock at a 15% discount, with a 24-month look-back.
• Save for your future with our retirement plans that vary by region and country.
• Competitive salaries.