Design Verification Engineer

We are seeking a Design Verification Engineer specializing in Simulation to join our team at Cisco. As a Design Verification Engineer, you will be responsible for developing and executing verification strategies to ensure the correctness and performance of complex hardware designs. Your primary focus will be on emulation platforms to accelerate verification cycles and improve coverage.

Key Responsibilities:

• Develop and implement verification plans and test benches using Simulation tools and methodologies.
• Collaborate with design and validation teams to identify verification requirements and coverage goals.
• Utilize emulation platforms to run large-scale verification tests and debug design issues.
• Analyse verification results, identify bugs, and work closely with design engineers to resolve issues.
• Maintain and enhance verification infrastructure and automation frameworks.
• Document verification processes, test cases, and results to ensure traceability and reproducibility.
• Stay current with emerging verification technologies and best practices, particularly in emulation.
• Mentor junior engineers and contribute to team knowledge sharing.

Minimum Qualifications:

• Bachelors + 7 years of related experience, or Masters + 4 years of related experience, or PhD + 1 year of related experience
• Strong experience in Design verification methodologies using UVM or OVM
• Relevant experience in design verification with a strong emphasis Test Methodologies
• Experience in Networking (Ethernet, AXI, AMBA, PCIe etc)