ASIC TOP Floorplan Design Engineer

We are now looking for an ASIC Top Floorplan Design Engineer. NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the world’s leading SoC's and GPU's.

This position offers you a unique opportunity to craft and to influence the design and development of the next generation GPU and SoC, allowing you to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.

What you will be doing:

• Working with architects, design leads, physical design leads and package leads, you will develop, craft and optimize floorplans during early chip development.
• Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan improvement opportunities.
• Solve timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical implementation decisions.
• You will build tools and improve existing infrastructure using AI extensively to optimize chip area and speed of execution.

What we need to see:

• Master’s degree in electrical engineering, Computer Science, or Computer Engineering and 1+ year equivalent work/learning experience.
• Experience in Verilog, System Verilog or similar HVL.
• Experience with CAD and physical design methodologies (flow and tool development), chip floorplan, power/clock distribution, packaging, P&R and timing closure.
• Strong communication and interpersonal skills and ability & desire to work as a great teammate should be displayed in your interview.
• Python, Perl and C/C++ programming language experience.
• Experience using AI coding assistants like Cursor or Github copilot or Windchill

Ways to stand out from the crowd:

• Experience in driving development of large-scale ASIC floorplan is a huge plus.
• Experience building large projects from the ground up using AI tools.
• Good command of spoken English