Description
Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.
You are an early-career engineer ready to make your mark in semiconductor design. You have spent your academic years drawn to digital design that requires proof, not just simulation. When you see a spec, you think about corner cases and what could break. You have written Verilog or SystemVerilog, debugged logic that did not behave as expected, and you are comfortable in a Unix terminal. Formal verification might be new to you, but the rigor makes sense. You learn by doing, ask questions when stuck, and you do not mind being the person who finds the bug everyone else missed.
Responsibilities
- Learn the latest formal verification methodology from experts and apply your learnings to live projects.
- Work with a team of seasoned FV engineers and execute validation as per defined plans.
- Support quality improvements and contribute insights that help enhance verification tool capabilities.
- Write and refine assertions in SystemVerilog Assertions (SVA) to capture design intent and uncover edge-case failures.
- Script verification flows using Python, Perl, or Tcl to automate repetitive tasks and improve team productivity in Unix/Linux environments.
The Impact You Will Have
- Help catch critical design bugs before tapeout that would otherwise cost months and millions to fix in silicon.
- Contribute to the quality and reliability of Synopsys IP and EDA tools that power semiconductor development across the industry.
- Accelerate verification closure on complex designs by applying formal methods that simulation alone cannot cover.
- Strengthen the formal verification methodology at Synopsys by bringing fresh perspectives and identifying gaps in existing flows.
Requirements
- Master’s degree in Electronics, Electrical, Instrumentation, or a related engineering discipline. (2026 Fresh Masters Grad Expected).
- 0 to 2 years of experience in digital design, verification, or related semiconductor work (internships, projects, and coursework count).
- Strong understanding of computer architecture and digital design fundamentals including state machines, pipelining, and timing.
- Hands-on experience with hardware description languages, Verilog or SystemVerilog preferred.
- Proficiency in at least one scripting language such as Python, Perl, or Tcl, and comfort working in Unix or Linux environments.
- Solid academic performance with relevant coursework or project work in VLSI, digital design, or verification.
- Experience with formal verification tools, assertion languages, or model checking is a strong plus.
Benefits
- Comprehensive medical and healthcare plans that work for you and your family.
- In addition to company holidays, we have ETO and FTO Programs.
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
- Purchase Synopsys common stock at a 15% discount, with a 24-month look-back.
- Save for your future with our retirement plans that vary by region and country.
- Competitive salaries.