Description
The Common Hardware Group (CHG) at Cisco is looking for a Package Design Lead to drive complex package design programs from planning and optimization to execution. You will lead and grow the San Jose package design team, mentoring engineers and developing future package leads while collaborating closely with layout, SI/PI, silicon architecture, and manufacturing partners.
Responsibilities:
- Lead complex package design programs, planning and driving schedules from concept through implementation and tapeout.
- Optimize package pinouts, stack-ups, power distribution, and high-speed routing, balancing performance, manufacturability, and reliability.
- Collaborate with silicon floor planning, signal integrity (SI), and power integrity (PI) teams to ensure design quality and system-level alignment.
- Work closely with layout editors and implementation teams to deliver high-quality package layouts aligned with interface and manufacturing requirements.
- Serve as the technical and organizational leader of the San Jose package design team, providing direction, mentorship, and technical guidance to engineers.
- Develop and grow package design capability within the team, mentoring engineers and enabling them to take ownership of increasingly complex package programs.
- Coordinate resources across designers, layout editors, and contractors to support efficient project execution.
- Enhance package design methodologies and partner with vendors to improve product quality and efficiency.
- Drive innovation in package solutions for Cisco’s next-generation ASIC platforms.
Minimum Qualifications:
- Bachelor’s degree in electrical engineering or a related field with 12+ years of work experience or Master’s degree in Electrical Engineering or a related field with 8+ years of work experience.
- Experience in high-speed package design, including signal integrity considerations and power distribution networks (PDN).
- Experience with industry-standard EDA tools for package layout and design.
- Experience with technical leadership in complex hardware or silicon development programs.
Preferred Qualifications:
- Extensive experience in ASIC package design, including pinout optimization and high-speed routing.
- Knowledge of silicon floor planning and strong collaboration with SI and PI teams.
- Experience leading or mentoring engineering teams and developing technical talent.
- Experience coordinating complex cross-functional hardware development programs.
- Experience with testing and measurement equipment (oscilloscopes, TDR/VNA analyzers).
- Experience with scripting languages such as Python, Perl, TCL, or shell programming.
The starting salary range for this position is $214,100.00 to $309,800.00, and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation, equity, or benefits.