Senior ASIC Design Engineer

NVIDIA is looking for a Senior ASIC Design Engineer to join the Memory Subsystem Team.

As a member of the Memory Subsystem Design team, you will collaborate with architects, design verification, formal verification, and physical design teams to deliver a world-class solution. NVIDIA SOC Interconnects, ordering controllers, and memory accelerators are among the industry's most sophisticated due to complex area, latency, power, bandwidth, and quality-of-service requirements.

In this position, you will be responsible for the micro-architecture and design, including RTL design, synthesis, and timing analysis using innovative CAD tools and the latest process technologies.

Requirements:

• BS or MS in Electrical Engineering or Computer Engineering or related degree (or equivalent experience)
• 5+ years of experience
• Experience with high-speed coherent interconnects, protocol bridges, hardware-managed coherency, and system-level caches is a plus
• Experience with multiple clock domains and asynchronous interfaces is a plus
• Knowledge of industry specifications like CHI/CXL/PCI-E is a plus
• Strong proficiency in Verilog or VHDL
• Scripting language like PERL

Benefits:

• Base salary range: 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4
• Equity and benefits