Description
The Common Hardware Group at Cisco is looking for an ASIC Implementation Technical Lead with a focus on Design-for-Test. You will work on designing, developing, and testing complex ASICs for Cisco's core Switching, Routing, and Wireless products.
Key contributions:
- Manage the definition, architecture, and design of high-performance ASICs
- Own applications or multiple complex functional areas
- Oversee reusable code and its applications
- Create re-usable code that promotes efficiencies in new ways
- Define verification strategies
- Coordinate with stakeholders to integrate into PD and DV flows
- Own infrastructure and testing environments
- Lead and design the building blocks of multiple channels
- Apply and drive the design methodology from conception to production
- Influence and collaborate with teams to ensure specifications and requirements are met
- Lead technical expertise of a physical design function
- Interface with vendors and design leads on full chip timing closure, PI, and PV
- Own the full electrical planning and specifications of electrical interfaces
- Develop multiple solutions, first test vehicles, and perform verification and validation
Minimum qualifications:
- Bachelor's or Master's degree in Electrical or Computer Engineering
- At least 12+ years of experience
- Prior experience with Jtag protocols, Scan insertion, and BIST architectures
- Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets
- Experience working with Gate level simulation, including timing-based simulations with sdf, debugging with VCS and other simulators
- Post-silicon validation and debug experience
- Scripting skills: Tcl, Python/Perl
Preferred qualifications:
- Verilog design experience – developing custom DFT logic & IP integration; familiarity with functional verification
- DFT CAD development – Test Architecture, Methodology, and Infrastructure