Applications Engineering, Staff Engineer

You are a passionate engineer with a keen interest in formal verification and EDA tool validation. You will join Synopsys, a company that drives innovations shaping the way we live and connect, particularly in the Era of Pervasive Intelligence.

Your role as a Staff Engineer in Applications Engineering involves:

• Developing and maintaining Assertion IP for complex bus protocols like AMBA family and memory interfaces
• Creating differentiating features and innovative methodologies for formal verification tools
• Validating advanced features of EDA tools such as Synopsys VC Formal
• Collaborating with cross-functional teams to define and enhance tool features
• Staying current with the latest formal verification methodologies and industry standards

The impact of your work will be:

• Ensuring the reliability and performance of industry-leading formal verification tools
• Driving quality improvements influencing customer success and satisfaction
• Contributing to faster time-to-market for advanced silicon solutions
• Empowering cross-functional teams with actionable insights and feedback

To succeed, you need:

• A Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related discipline
• 2–14 years of experience in formal verification or EDA tool validation
• Hands-on experience with formal verification tools like Synopsys VC Formal
• Proficiency in developing synthesizable code for assertion IPs and scripting languages like Python, Perl, and Tcl

You will be part of a dynamic engineering team focused on developing and validating world-class formal verification solutions.

Rewards and benefits include a comprehensive range of health, wellness, and financial offerings.