Description
We are looking for a Senior Mask Layout Design Engineer to join a growing team responsible for handling high-speed mixed-signal circuit designs.
Job Summary: As a Senior Mask Layout Design Engineer, you will perform physical layout for mixed-signal functions like PLLs, high-speed SerDes, and Analog to Digital converters in state-of-the-art sub-micron CMOS technologies using Cadence tools. You will work cross-functionally with ASIC and mixed-signal engineers to customize designs for integration in VLSI products.
Responsibilities:
- Perform physical layout for mixed-signal functions using Cadence tools
- Work cross-functionally with ASIC and mixed-signal engineers to customize designs
- Take part in floor planning, custom layout, and verifying against design rules and schematics
Requirements:
- BSEE or equivalent experience
- Minimum of 7+ years of industry experience in Mask and Layout Design
- Deep understanding of analog circuit layout concepts in submicron CMOS technologies
- Expertise with Cadence custom circuit design tools, particularly Virtuoso
- Experience with verification tools such as Dracula, Hercules, Calibre, and Primeyield
- Proficiency in scripting languages like Perl, Python, and Skill
- Knowledge of DRC and LVS checking flows, ability to customize decks
Salary: The expected base salary ranges for this position are: 132,000 USD – 207,000 USD for Level 4; and 148,000 USD – 235,750 USD for Level 5.
Benefits: You will also be eligible for equity and benefits.