Verification Engineer

As a Verification Engineer in NVIDIA's MMPLEX team, you will play a crucial role in ensuring the quality and functionality of our hardware IPs.

Responsibilities:

• Participate in the research of verification methodology to improve automation and productivity to produce NVIDIA's new high-quality products.
• Read IAS and design specs to understand the design requirement and build corresponding testplan. Review the testplan with arch/design engineers.
• Build block/IP testbench based on UVM methodology.
• Build test run and regression flow. Triage failures in regression and help designer root cause the bug.
• Work on building various metrics (passing rate, functional coverage, etc) and monitor its health.
• Take SOC verification on fullchip test environment for IPs.
• Analyse functional/code coverage result and identify the coverage holes. Work with design engineer to improve the coverage score.
• Deploy the advanced verification methodology and infrastructure of the SOC/IP.

Requirements:

• MS in electrical/computer engineering or equivalent experience.
• 5+ years (MS) working experience.
• Familiar with advance verification methodology, tools and flow.
• Fully experienced verification flow, including testplan, test, coverage model, testbench, BFM modeling.
• Deep understanding in Verilog and HVL (High-level Verification Language).

Preferred skills:

• Strong programming skills in Python and C/C++.
• Having good arch/design experience.
• At least good at one of the script programming languages: Perl, Shell, Ruby, Python.

NVIDIA offers competitive salaries and a generous benefits package.