Description
The Common Hardware Group (CHG) at Cisco is looking for a Hardware Design-for-Test (DFT) Engineer.
You will be responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug, and diagnostics needs of the designs.
Key responsibilities:
- Develop innovative DFT IP in collaboration with multi-functional teams
- Play a key role in full chip design integration with testability features coordinated in the RTL
- Work closely with design/design-verification and PD teams to enable integration and validation of Test logic
- Participate in creating innovative hardware DFT and physical design aspects for new silicon device models
- Craft solutions and debug with minimal mentorship
Requirements:
- Bachelor's or Master's Degree in Electrical or Computer Engineering
- 4-8 years of experience
- Knowledge of latest innovative trends in DFT, test, and silicon engineering
- Experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan
- Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime
- Verification skills in System Verilog, Logic Equivalency checking, and validating Test-timing of the design
- Experience working with Gate level simulation, debugging with VCS and other simulators
Preferred qualifications:
- Post-silicon validation and debug experience
- Ability to work with ATE patterns, P1687
- Strong verbal skills and ability to thrive in a multifaceted environment
- Scripting skills in Tcl, Python/Perl