Staff Verification Applications Engineer

We are seeking a highly experienced Staff Verification Applications Engineer to join our team at Synopsys in Hyderabad, Telangana, India.

You will work directly with customers running the most complex verification challenges in the industry, and what you solve will determine whether their tape-out happens on time. As a Staff Verification Applications Engineer, you will drive customer deployments of VCS and Verdi simulation and debug technology, working directly with design and verification teams to integrate tools into their existing flows.

Key responsibilities include:

• Driving customer deployments of VCS and Verdi simulation and debug technology
• Diagnosing and resolving complex technical issues across UVM testbenches, SVA assertions, Low Power UPF flows, and Gate Level Timing simulations
• Collaborating with global R&D and product teams to gather customer requirements, reproduce issues, and influence the product roadmap based on real deployment feedback
• Leading competitive engagements by running benchmarks, demonstrating VCS/Verdi advantages, and helping customers evaluate simulation performance and debug efficiency
• Developing and optimizing automation scripts in Perl, Tcl, Python, Shell, and Make to improve customer productivity and streamline verification workflows
• Interfacing directly with customers, product validation teams, and R&D to propose solutions, suggest product improvements, and close the loop on deployment challenges
• Supporting customers adopting AI-driven verification productivity tools and advanced simulation features as part of their methodology evolution

The impact you will have:

• Enabling customers to close verification faster and hit first-pass silicon by deploying simulation technology that actually scales to their design complexity
• Reducing time-to-tapeout for semiconductor companies building everything from mobile SoCs to automotive safety-critical designs
• Shaping the VCS and Verdi product roadmap by surfacing real customer pain points and competitive gaps that R&D needs to address
• Driving adoption of advanced verification methodologies including UVM, Low Power, and Gate Level Timing simulation across global customer accounts
• Building long-term customer relationships that turn Synopsys tools into the backbone of their verification infrastructure
• Accelerating the industry's shift toward AI-augmented verification by helping customers integrate and adopt new productivity capabilities
• Strengthening Synopsys' competitive position in simulation and debug by winning benchmarks and proving performance in head-to-head evaluations

Requirements:

• Bachelor's or Master's degree in Electronics Engineering or related field with 5-12 years of hands-on experience in verification or applications engineering
• Strong working knowledge of VCS simulation technology and Verdi debug platform, or equivalent simulation and waveform debug tools
• Deep expertise in SystemVerilog, UVM, SVA, and verification methodologies applied to real RTL designs
• Proven experience with Low Power UPF flows and Gate Level Timing simulations in customer or product validation environments
• Advanced scripting ability in Perl, Tcl, Python, Shell, and Make for automation and flow development
• Solid understanding of digital design fundamentals, Verilog, VHDL, and UNIX/Linux environments
• Exposure to DPI, C/C++, SystemC, Functional Safety, or GenAI technologies is a plus

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.