High Speed IP PHY/USB Applications Principal Engineer

You will be a High Speed IP PHY/USB Applications Principal Engineer at Synopsys, working on providing technical support to customers integrating DesignWare USB Mixed Signal PHY IP.

Your responsibilities will include:

• Providing technical support to customers integrating DesignWare USB Mixed Signal PHY IP from initial integration through silicon bring-up and debug
• Troubleshooting customer issues across synthesis, static timing analysis, design-for-test, and clock domain crossing in USB PHY and SoC integration contexts
• Guiding customers through USB 2.0, USB 3.x, and Type-C implementation considerations and design tradeoffs, and helping define bring-up and debug plans that reduce time-to-silicon
• Collaborating closely with the Korea AE team and Synopsys R&D and product teams to escalate complex issues, drive root-cause analysis, and ensure timely closure during critical milestones
• Contributing to customer support coverage for other high-speed interface PHY IP in collaboration with colleagues, leveraging similar integration and debug fundamentals
• Delivering technical presentations and integration best practices to customer engineering teams during design reviews and key program checkpoints
• Traveling occasionally to customer sites across Korea and the region to support critical milestones

The impact you will have:

• Enabling customer success on high-stakes tapeouts by resolving USB PHY integration issues that would otherwise delay schedules
• Reducing time-to-silicon by providing clear, actionable guidance during integration, constraints closure, and silicon bring-up
• Building deep technical relationships with leading semiconductor companies in Korea as their trusted advisor
• Shaping future IP releases by channeling real customer pain points back into the product team
• Expanding Synopsys footprint in customer accounts through technical depth, responsiveness, and cross-team collaboration

To be successful in this role, you will need:

• A Bachelor's or Master's in Electrical Engineering or Computer Engineering with 10 to 20+ years of ASIC design, verification, or SoC integration experience
• Strong working knowledge of synthesis, static timing analysis, design-for-test, and clock domain crossing
• Ability to work independently and drive ambiguous, customer-driven issues to resolution
• Excellent communication skills in Korean and English, able to explain complex concepts clearly
• USB 2.0, USB 3.x, Type-C, or USB PHY integration experience is a strong plus
• Broader high-speed interface background is a plus and helps with collaborative cross-IP support coverage
• Willingness to travel occasionally within Korea and the region