ASIC Design / Verification, Manager-Sr Manager

We are seeking a seasoned professional to lead our ASIC Design and Verification team at Synopsys in Hsinchu, Taiwan.

As a Manager or Senior Manager, you will be responsible for designing and verifying IP cores and/or SOCs, leading a team, and collaborating with global teams.

Key Responsibilities:

• Specify, design, and implement IP Design and/or Verification environments for synthesizable DesignWare cores
• Lead a team, guiding them towards the closure of day-to-day design and/or verification activities
• Work closely with RTL designers, Architects, and Verification Engineers as part of a global team
• Understand design specifications and develop RTL code, test plans, and testbenches at both unit and system levels
• Ensure product release milestones are met through effective regression debug triaging and verification activities
• Contribute to the development and implementation of NextGen DesignWare HBM IPs

Requirements:

• BS/MS in EE/EC/VLSI with 15+ years of relevant experience in the verification of IP cores and/or SOC
• Experience in leading a team of engineers and guiding them towards achieving project milestones
• Hands-on experience in RTL design and/or verification of complex designs at the IP or SoC level
• Strong knowledge of Verilog/System Verilog and experience in developing testbenches in UVM environments
• Experience with memory protocols like HBM/DDR/LPDDR and familiarity with IP design and verification tools
• Proficiency in Perl/Python-based automation and excellent communication and problem-solving skills

Benefits:

• Comprehensive medical and healthcare plans
• Time away programs, including ETO and FTO
• Family support, including maternity and paternity leave, parenting resources, adoption and surrogacy assistance
• ESPP program, allowing purchase of Synopsys common stock at a 15% discount
• Retirement plans that vary by region and country
• Competitive salaries