Sr/Staff Application Engineer(Verification tools)

As a Senior Application Engineer (Verification tools) at Synopsys, you will provide advanced technical support for EDA Design & Verifications tools, addressing complex customer issues and ensuring customer satisfaction.

Your responsibilities will include:

• Taking ownership of tool migrations, bringing up verification environments, and Verification IPs
• Collaborating with worldwide Application Engineers, R&D teams, and customers to understand requirements, address escalations, and ensure successful adoption of solutions and tool development
• Actively contributing to strategies that secure and expand market share by understanding the competitive landscape and building strong customer relationships
• Developing and sharing technical documentation, leading knowledge transfer, and mentoring junior team members

To be successful in this role, you will need:

• 1+ years of experience in Design and Verification or as an Application Engineer in the Verification Field
• Good knowledge of Verilog, UVM, System Verilog, VHDL, and UPF
• Expertise in Design and Verification, Verification IPs (AMBA VIP), Static and/or Dynamic Verification
• Excellent communication skills in English, with the ability to work cross-functionally and cross-regionally
• Passion for using new tools and features, as well as AI-related tools
• Ability to manage relationships with both customers and internal stakeholders
• Demonstrated leadership in mentoring, onboarding, or leading technical initiatives