R&D Engineering, Principal Engineer

Synopsys software engineers are key enablers in the world of Electronic Design Automation (EDA), developing and maintaining software used in chip design, verification and manufacturing. They work on assignments like designing, developing, and troubleshooting software, leveraging the state-of-the-art technologies like AI/ML, GenAI and Cloud. Their critical contributions enable world-wide EDA designers to extend the frontiers of semiconductors and chip development.

As a Principal Engineer, you will work on standard cell libraries that power some of the most advanced semiconductor designs in production today. The problems are hard, the nodes are bleeding-edge, and the work you do will directly affect whether a chip meets its performance target or not.

Responsibilities

• Own timing signoff methodology for standard cell libraries across TSMC N3, N2, N5, N7, and derivative nodes, defining setup, hold, recovery, removal, pulse-width, and noise margins that hold up in silicon
• Develop and validate multi-corner, multi-mode signoff flows for low-VDD, high-performance, and AI/compute SoCs, accounting for AOCV, POCV, SOCV, aging effects, and dynamic voltage drop
• Drive correlation analysis between Liberty models, PrimeTime STA results, HSPICE simulations, and silicon measurements to improve timing prediction accuracy and close signoff gaps
• Debug critical customer-reported timing issues, root-cause discrepancies between characterization, signoff, and deployment, and define corrective actions that prevent recurrence
• Build automation infrastructure in Python and Tcl to scale signoff validation, quality checks, and methodology deployment across multiple library releases
• Collaborate with characterization, CAD, modeling, EDA vendors, and foundry partners to influence signoff methodology direction and resolve advanced-node timing challenges
• Create technical documentation, best-practice guidelines, and deployment recommendations that internal teams and external customers rely on for signoff success

The Impact You Will Have

• Your signoff methodologies will define how Synopsys standard cell libraries are validated and deployed across dozens of customer tape-outs on the most advanced nodes in production
• You will directly improve the accuracy of timing models that determine whether high-performance AI and compute chips meet their frequency, power, and yield targets
• Your correlation work will close the gap between what we predict in Liberty and what customers measure in silicon, reducing over-design margin and enabling better PPA
• You will resolve customer escalations that are blocking tape-out schedules, turning critical timing failures into understood, fixable methodology gaps
• Your automation and QA infrastructure will scale signoff validation across multiple nodes, reducing characterization cycle time and catching issues before libraries ship
• You will mentor senior engineers and technical leads, raising the bar for timing signoff expertise across the standard cell library development organization
• Your technical leadership will shape how Synopsys approaches variation-aware timing, low-VDD signoff, and advanced-node methodology for the next generation of process technologies

Requirements

• 15+ years of semiconductor industry experience with significant depth in timing signoff, static timing analysis, and standard cell library development
• Recognized expertise in STA and signoff methodologies for advanced process nodes, ideally including direct experience with TSMC N7, N5, N3, or equivalent
• Deep hands-on proficiency with Synopsys PrimeTime, PrimeTime-SI, SiliconSmart or Liberate, HSPICE, Spectre, and FineSim
• Strong understanding of Liberty modeling, LVF, AOCV, POCV, SOCV, statistical timing, and variation-aware signoff techniques
• Proven track record defining and deploying signoff methodologies that have been adopted across multiple products, customers, or business units
• Expert-level automation skills in Python and Tcl, with experience building scalable signoff and QA infrastructure in Linux environments
• Experience correlating STA results, SPICE simulations, parasitic extraction, and silicon measurements to drive signoff accuracy and resolve discrepancies