Principal Digital Methodology Engineer - Design for Testability (DFT)

You will work on methodologies that define how the world's most complex chips get tested. As a Principal Digital Methodology Engineer - Design for Testability (DFT), you will define and drive DFT methodologies for next-generation ASIC and SoC designs across strategic customer programs, translating architecture decisions into deployable best practices.

Key responsibilities include:

• Leading deployment of advanced test solutions including scan compression, hierarchical DFT, IEEE 1500 wrappers, IJTAG instrumentation networks, and embedded test IP across multi-billion-gate designs
• Architecting scalable test access infrastructures using IEEE 1149.1, IEEE 1149.6, IEEE 1687, and IEEE 1500 standards for complex multi-die and chiplet-based systems
• Developing automation frameworks, signoff criteria, and reusable methodology packages using Tcl, Python, and Perl that accelerate adoption across business units
• Serving as technical leader and subject matter expert for Synopsys TestMAX DFT, TestMAX ATPG, diagnosis, and silicon lifecycle solutions in customer engagements and internal escalations

The ideal candidate will have:

• Bachelor's or Master's in Electrical Engineering, Computer Engineering, or related field
• 15+ years in semiconductor or EDA industry with at least 5 years focused on DFT architecture, ATPG, and manufacturing test methodologies
• Demonstrated expertise architecting and implementing DFT solutions for large-scale ASIC and SoC designs, including successful tapeouts
• Hands-on experience with Synopsys TestMAX DFT and TestMAX ATPG solutions in production design environments

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.