Principal Physical Design Engineer

You will be a Principal Physical Design Engineer at Synopsys, working on implementation challenges that define what is possible at 5nm and below.

Overview As a Principal Physical Design Engineer, you will lead physical design engagements for strategic semiconductor customers working on advanced-node designs, from floorplanning through signoff. You will develop and optimize RTL-to-GDSII methodologies that improve PPA, reduce runtime, and accelerate design closure for production tapeouts.

Responsibilities

• Lead physical design engagements for strategic semiconductor customers working on advanced-node designs, from floorplanning through signoff
• Develop and optimize RTL-to-GDSII methodologies that improve PPA, reduce runtime, and accelerate design closure for production tapeouts
• Build automation frameworks using Python and Tcl that solve real productivity bottlenecks in placement, CTS, routing, and timing closure workflows
• Collaborate with Product Engineering and global R&D teams to validate new Synopsys implementation technologies and translate customer feedback into product requirements
• Drive technical evaluations and benchmarking programs that demonstrate measurable improvements in customer design metrics
• Support advanced-node enablement and DTCO initiatives in partnership with foundries and customer design teams
• Mentor engineers across the Korea team and contribute to technical leadership on methodology development and customer engagement strategy

Requirements

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field
• 15+ years of hands-on experience in semiconductor physical design, implementation methodologies, or EDA development
• Deep expertise across the RTL-to-GDSII flow including floorplanning, placement optimization, clock tree synthesis, routing, timing closure, power optimization, and physical verification
• Strong proficiency in Python and Tcl for building automation frameworks and productivity tools
• Demonstrated experience working directly with semiconductor customers to solve complex implementation challenges and deploy methodologies in production environments
• Fluency in Korean and English with the ability to lead technical discussions, present to executive stakeholders, and document methodologies in both languages
• Experience with Fusion Compiler, IC Compiler II, PrimeTime, or equivalent implementation and signoff tools is a strong plus

Benefits

• Comprehensive medical and healthcare plans that work for you and your family
• Time away, including company holidays, ETO, and FTO Programs
• Family support, including maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
• ESPP: purchase Synopsys common stock at a 15% discount, with a 24-month look-back
• Retirement plans that vary by region and country
• Competitive salaries