Description
Join the Cisco SiliconOne team in Bangalore, India, and be part of crafting groundbreaking Enterprise and Service Provider solutions. As a Physical Design Engineer, you will create next-generation networking chips in advanced process nodes.
Your responsibilities include:
- Driving the backend process through RTL 2 GDS Implementation flow
- Hierarchical floor planning, place & route, timing closure, power integrity, static timing verification, physical verification, and equivalence checks
- Performance and die size optimization
Requirements:
- Bachelor's or Master's Degree in Electrical or Computer Engineering with 4+ years of experience
- Experience with ASIC physical implementation, including floor planning, clock and power distribution, global signal planning, I/O planning, and hard IP integration
- Knowledge of hierarchical design implementation approach, timing closure, and physical convergence
- Experience with automation scripts within STA tools for methodology development
- Power integrity analysis and STA setup, convergence methodology, reviews, and sign-off for multi-mode and multi-corner designs
Preferred qualifications:
- Analyzing current generation quality and efficiency gaps to identify incremental or evolutionary changes
- Good understanding of different CTS strategies and providing feedback to the implementation team
- Driving methodologies and 'best known methods' to streamline and automate physical design work
- Experience with timing ECO implementation strategy development and convergence
At Cisco, you're part of a team that's revolutionizing how data and infrastructure connect and protect organizations in the AI era.