Description
We are looking for a Senior Mask Layout Design Engineer to join our growing and dynamic team. As a Senior Mask Layout Design Engineer, you will be responsible for performing physical layout for mixed-signal functions like PLL's, high speed SerDes, Analog to Digital converters, ESD structures designs in state-of-the-art sub-micron CMOS technologies using Cadence tools.
You will work cross functionally with ASIC and mixed-signal engineers to customize designs for integration in VLSI products. You will also take part in floor planning, custom layout and verifying against design rules and schematics.
To be successful in this role, you will need to have a BSEE or equivalent experience, minimum of 7+ years industry experience in Mask and Layout Design, deep understanding of analog circuit layout concepts in submicron CMOS technologies, and be an authority with Cadence custom circuit design tools - particularly virtuoso.
You will also need to have experience running and debugging with verification tools such as Dracula, Hercules, Calibre, and Primeyield, be able to work effectively in a team, have good interpersonal skills, enthusiasm and positive energy, and be proficient in scripting languages like perl, python, skill etc.
You will also be eligible for equity and benefits.