ASIC Design Engineer - New College Grad 2026

We are seeking a Logic Design Engineer to join our CPU Logic Design Team.

As a member of our team, you will be responsible for CPU on-chip interconnect network, coherency and last-level caches, focusing on tasks such as micro-architectural definition, RTL coding, logic debug, synthesis and timing closure, supporting verification and implementation.

Responsibilities:

• Own and be responsible for crafting and timely delivery of a specific unit on the chip.
• Write readable high-performance and low-power RTL, perform synthesis and timing closure, and create design documentation.
• Collaborate with the verification team to verify the correctness of your unit.
• Work with implementation to achieve timing, area, performance, and power goals.
• Assist with timing closure of super units.

Requirements:

• Recent graduate with a BS or MS degree in Electrical Engineering, Computer Engineering, or Computer Science (or equivalent experience).
• Experience in processor or other related high-performance semiconductor designs.
• Verilog expertise required, as well as a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up, and lab debug.
• Effective communication and interpersonal skills are required, along with experience working in a dynamic, global team.
• A strong background in computer architecture, cache coherency, or high-speed interconnects is preferred.

You will also be eligible for equity and benefits.