Staff Verification Applications Engineer

You will engineer the future with Synopsys, the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. As a Staff Verification Applications Engineer, you will work directly with customers running the most complex verification challenges in the industry.

Responsibilities

• Drive customer deployments of VCS and Verdi simulation and debug technology, working directly with design and verification teams to integrate tools into their existing flows
• Diagnose and resolve complex technical issues across UVM testbenches, SVA assertions, Low Power UPF flows, and Gate Level Timing simulations
• Collaborate with global R&D and product teams to gather customer requirements, reproduce issues, and influence the product roadmap based on real deployment feedback
• Lead competitive engagements by running benchmarks, demonstrating VCS/Verdi advantages, and helping customers evaluate simulation performance and debug efficiency
• Develop and optimize automation scripts in Perl, Tcl, Python, Shell, and Make to improve customer productivity and streamline verification workflows
• Interface directly with customers, product validation teams, and R&D to propose solutions, suggest product improvements, and close the loop on deployment challenges
• Support customers adopting AI-driven verification productivity tools and advanced simulation features as part of their methodology evolution

The Impact You Will Have

• Enable customers to close verification faster and hit first-pass silicon by deploying simulation technology that actually scales to their design complexity
• Reduce time-to-tapeout for semiconductor companies building everything from mobile SoCs to automotive safety-critical designs
• Shape the VCS and Verdi product roadmap by surfacing real customer pain points and competitive gaps that R&D needs to address
• Drive adoption of advanced verification methodologies including UVM, Low Power, and Gate Level Timing simulation across global customer accounts
• Build long-term customer relationships that turn Synopsys tools into the backbone of their verification infrastructure
• Accelerate the industry's shift toward AI-augmented verification by helping customers integrate and adopt new productivity capabilities
• Strengthen Synopsys' competitive position in simulation and debug by winning benchmarks and proving performance in head-to-head evaluations

Requirements

• Bachelor's or Master's degree in Electronics Engineering or related field with 5-12 years of hands-on experience in verification or applications engineering
• Strong working knowledge of VCS simulation technology and Verdi debug platform, or equivalent simulation and waveform debug tools
• Deep expertise in SystemVerilog, UVM, SVA, and verification methodologies applied to real RTL designs
• Proven experience with Low Power UPF flows and Gate Level Timing simulations in customer or product validation environments
• Advanced scripting ability in Perl, Tcl, Python, Shell, and Make for automation and flow development
• Solid understanding of digital design fundamentals, Verilog, VHDL, and UNIX/Linux environments
• Exposure to DPI, C/C++, SystemC, Functional Safety, or GenAI technologies is a plus