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From the employer's careers site First seen 18 May 2026 · Still live on 31 Oct 2026

Senior Mixed Signal Design Engineer

NVIDIA Santa Clara On-site senior full-time

The employer hasn't listed a salary.

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Description

This is a diverse team working with innovative, groundbreaking technology. As a member of our Mixed Signal team, you will lead the design of CMOS high-speed interface circuits and mixed-signal circuits. Strong hands-on experience in the lab with silicon validation, debugging, characterization, and bring up.

Responsibilities:

  • Lead design and implementation of high-speed interface circuits
  • Design projects include high-speed transceivers and high-frequency PLLs
  • Design, simulation, and verification of mixed-signal circuits
  • Supervise closely IC circuit/mask designers, provide floorplan and layout guidelines
  • Support lab characterization of silicon
  • Tackle challenges of circuit design in deep submicron CMOS
  • Take designs through implementation and productization
  • Work with multi-functional teams

Requirements:

  • MS in Electrical Engineering or equivalent experience
  • 4+ years of design experience in CMOS analog/mixed-signal circuit design
  • Solid understanding of Cadence custom design tools, circuit simulator, timing analysis tool
  • A great teammate with good interpersonal skills
  • Proven experience in crafting and mentoring designers
  • Extensive experience in Tx, Rx, CDR, PLL for high-speed IO interfaces
  • In-depth understanding of deep submicron CMOS process and related circuit design issues
  • Experience in silicon bring-up, debugging, and use of lab instrumentation is required
  • Knowledge in system-level timing budget, signal integrity, and power integrity is a plus
  • Experience in Verilog, Matlab, Primetime, Nanotime

You will also be eligible for equity and benefits.

Skills

Required

  • MS in Electrical Engineering
  • Cadence custom design tools
  • Circuit simulator
  • Timing analysis tool
  • Verilog
  • Matlab
  • Primetime
  • Nanotime

Nice to have

  • Tx, Rx, CDR, PLL for high-speed IO interfaces
  • Deep submicron CMOS process
  • System-level timing budget
  • Signal integrity
  • Power integrity
Apply on NVIDIA