Description
Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.
You have spent years proving that silicon actually works the way the spec says it should, and you know the difference between a testbench that catches bugs and one that just makes coverage numbers look good. Verification is not a checkbox exercise for you. It is the discipline of thinking through every edge case, every protocol violation, every timing corner that could turn a tapeout into a respin, and building the infrastructure to catch those problems before they become expensive.
At Synopsys, you will work on IP that powers the chips inside the devices changing how the world connects, computes, and moves.
Responsibilities
- Develop and validate verification environments for high-bandwidth interface IP from functional specifications through coverage closure
- Write test cases, assertions, and checkers in SystemVerilog to ensure comprehensive functional coverage
- Debug RTL, gate-level, and co-simulations involving real signal modeling for analog mixed-signal designs using VCS and Verdi
- Drive coverage analysis and closure across code, functional, and assertion metrics
- Participate in technical and peer reviews to ensure verification quality and process adherence
- Collaborate with design, architecture, and silicon validation teams to identify and resolve issues early
Requirements
- Bachelor's, Master's, or PhD in Electronics Engineering, Electromechanics, Telecommunications, or related field
- 2+ years of hands-on design verification experience, ideally on digital or mixed-signal IP
- Strong proficiency with SystemVerilog, UVM, and industry-standard verification methodologies
- Experience with VCS and Verdi for simulation and debug
- Solid understanding of verification planning, coverage-driven verification, and assertion-based verification
- Familiarity with formal verification tools like vc_formal is a plus
- Scripting experience in Perl, TCL, or Python is a plus