Description
Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.
You have spent over a decade taking complex SoCs from RTL to silicon, and you know that the difference between a chip that meets PPA and one that doesn't often comes down to decisions made during floorplanning or a CTS strategy that accounts for what the foundry PDK will actually give you at 3nm. You are the engineer who sees congestion coming three steps ahead and adjusts before it becomes a crisis that delays tapeout.
What You'll Be Doing
- Lead full-chip and block-level physical implementation from RTL through GDSII tapeout on advanced-node designs at 5nm, 3nm, and below
- Define and execute floorplanning, power planning, placement, clock tree synthesis, routing, and signoff strategies that hit PPA targets
- Drive timing closure, power optimization, congestion reduction, and area improvement using Fusion Compiler, PrimeTime, and StarRC
- Perform and review static timing analysis, ECO implementation, IR-drop analysis, electromigration checks, and physical verification using IC Validator
- Work directly with semiconductor customers to enable their success, troubleshoot design challenges, and deliver technical workshops and methodology guidance
- Develop automation scripts and flows using Python, Tcl, and shell scripting to improve design productivity and methodology efficiency
- Leverage AI and ML-based physical design technologies including DSO.ai and Fusion Compiler optimizations to accelerate closure and explore the design space
The Impact You Will Have
- Enable customer tapeouts on the most advanced process nodes in the industry, directly influencing the success of next-generation AI, mobile, and high-performance computing chips
- Establish physical design methodologies and best practices that scale across large SoC programs and improve turnaround time for multi-billion transistor designs
- Translate real-world design challenges into actionable requirements that shape the roadmap for Synopsys implementation and signoff tools
- Mentor and elevate junior engineers, building technical depth across the team and raising the bar for design closure strategies
- Deliver designs that meet aggressive PPA targets and tapeout schedules, proving out methodologies that customers will adopt across their portfolios
- Drive automation and flow innovation that reduces manual effort, catches issues earlier, and makes complex physical design more predictable
- Influence foundry engagement and tool development by surfacing what works and what breaks at the cutting edge of semiconductor technology
What You'll Need
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field
- 10 to 15+ years of hands-on ASIC or SoC physical design experience with a proven track record of multiple successful tapeouts at advanced process nodes
- Deep expertise in floorplanning, power planning, place and route, clock tree synthesis, timing closure, and physical verification including DRC and LVS
- Strong working knowledge of IR-drop analysis, electromigration analysis, and ECO methodologies for late-stage design fixes
- Proficiency in scripting languages including Python, Tcl, Perl, or shell for automation and flow development
- Experience with Synopsys tools such as Fusion Compiler, PrimeTime, IC Validator, StarRC, Formality, and PrimePower is a strong plus
- Familiarity with foundry technologies from TSMC, Samsung, or Intel and an understanding of what changes at 5nm and below is highly valued