Senior Mask Layout Design Engineer

NVIDIA is looking for a Senior Mask Layout Design Engineer to join their team. The successful candidate will be responsible for performing physical layout for mixed-signal functions, working cross-functionally with ASIC and mixed-signal engineers, and taking part in floor planning, custom layout, and verifying against design rules and schematics.

Responsibilities:

• Performing physical layout for mixed-signal functions like PLL's, high-speed SerDes, Analog to Digital converters, ESD structures designs in state-of-the-art sub-micron CMOS technologies using Cadence tools.
• Working cross-functionally with ASIC and mixed-signal engineers to customize designs for integration in VLSI products.
• Taking part in floor planning, custom layout, and verifying against design rules and schematics.

Requirements:

• BSEE or equivalent experience.
• Minimum of 7+ years industry experience in Mask and Layout Design.
• Deep understanding of analog circuit layout concepts in submicron CMOS technologies.
• Authority with Cadence custom circuit design tools, particularly Virtuoso.
• Experience running and debugging with verification tools such as Dracula, Hercules, Calibre, and Primeyield.
• Ability to work effectively in a team, good interpersonal skills, enthusiasm, and positive energy.
• Proficiency in scripting languages like Perl, Python, Skill, etc.
• Knowledge of DRC and LVS checking flows, ability to customize decks.