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NVIDIA

ASIC Engineer

NVIDIA
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mid full-time $116,000 - $189,750 for Level 2 and $136,000 - $218,500 for

First indexed 11 Sept 2026

Description

We are seeking a top-notch ASIC engineer to join our Clocks team, responsible for crafting all aspects of GPU and CPU clocking. The team collaborates with various teams to understand clocking requirements, design the physical floorplan of the chip, and explain the programming model to the software team.

As an ASIC engineer, you will architect the clock domain to satisfy functional, physical, and testing design requirements. You will engage with multiple teams to design GPU or CPU clocks, improve Power, Performance, and Area (PPA) of innovative NVIDIA chips, and collaborate with Physical design and timing teams to evaluate clocking concerns.

Responsibilities:

  • Architect the clock domain to satisfy functional, physical, and testing design requirements
  • Engage with multiple teams to design GPU or CPU clocks
  • Improve Power, Performance, and Area (PPA) of innovative NVIDIA chips
  • Collaborate with Physical design and timing teams to evaluate clocking concerns
  • Deliver clock RTL information to GPU, CPU, and SOC verification teams, timing and DFT teams
  • Participate in the end-to-end cycle of ASIC execution

Requirements:

  • BS in Electrical Engineering or equivalent experience (MS preferred)
  • 2+ years of relevant work experience
  • Deep understanding of logic optimization techniques and PPA trade-offs
  • Excellent interpersonal skills and ability to collaborate with multiple teams
  • Experience in RTL design (Verilog), verification, and logic synthesis
  • Strong coding skills in Python or other industry-standard scripting languages

Preferred qualifications:

  • Experience with clocks controller, clocks logic design
  • Understanding of system-level artifacts like power, noise, etc.
  • Experience with scalable designs and architecture
  • Hands-on silicon debug experience

We offer competitive salaries and a generous benefits package. The base salary range is $116,000 - $189,750 for Level 2 and $136,000 - $218,500 for Level 3.

This listing is enriched and indexed by YubHub. To apply, use the employer's original posting: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/ASIC-Design-Engineer---Clocks-IP_JR2025580