SOC Engineer, Senior Staff

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

You are a passionate, detail-oriented engineer who thrives in collaborative and fast-paced environments. Your expertise in ASIC physical design makes you a go-to resource for solving complex challenges in silicon implementation. You enjoy mentoring others and sharing your knowledge, contributing to the technical growth of your team. You are driven by innovation and are always eager to stay at the forefront of technology, adapting quickly to new tools, methodologies, and process nodes.

Responsibilities

• Leading block-level and chip-level physical design activities from netlist through final implementation (RTL to GDSII).
• Driving floorplan: block shaping, power planning, pin and macro placement, special routing and ESD considerations to meet customer requirements
• Placement, clock tree synthesis, post cts and routing optimizations for timing, power, area, congestion and signal integrity to meet stringent project requirements.
• Signoff timing, EMIR and physical verification analysis and closure with ECOs
• Partnering with cross functional (RTL, Implementation, DFT, packaging, foundation IPs, MBIST) teams to achieve hardening closure goals.
• Developing and improving automation scripts and methodologies to increase physical design efficiency and quality.
• Investigating and resolving design, tool, flow and machine issues throughout the implementation cycle.
• Mentoring junior engineers and providing technical leadership across the team.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Strong experience in ASIC physical design and implementation.
• Hands-on knowledge of full physical design flow, including floorplan, optimizations, and signoff closure.
• Experience with advanced process nodes and IP integration challenges in complex SoCs.
• Strong understanding of STA, EMIR and physical verification concepts.
• Proficiency with industry-standard implementation and signoff tools such as Synopsys Fusion Compiler, PrimeTime, Redhawk SC, ICV and similar.
• Excellent written and verbal communication skills in English.
• Demonstrated ability to work effectively in cross-functional teams and build strong network relationships.

Benefits

• Comprehensive medical and healthcare plans that work for you and your family.
• In addition to company holidays, we have ETO and FTO Programs.
• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
• Purchase Synopsys common stock at a 15% discount, with a 24-month look-back.
• Save for your future with our retirement plans that vary by region and country.
• Competitive salaries.