SoC Design for Test (DFT) Engineer

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

As a SoC DFT Engineer in our System Solutions Group, you will be the guardian of silicon reliability. You will architect and build the test infrastructures that ensure our next-generation chips perform flawlessly in the real world.

You will own the DFT lifecycle from architecture definition to post-silicon reality. Working side-by-side with world-class Design, Verification, and Physical Design teams, you will push the boundaries of fault coverage, manufacturing quality, and production yield.

Responsibilities:

• Architect and build test infrastructures for next-generation chips
• Own the DFT lifecycle from architecture definition to post-silicon reality
• Collaborate with Design, Verification, and Physical Design teams
• Push the boundaries of fault coverage, manufacturing quality, and production yield

Requirements:

• BS/MS in Electrical Engineering, Computer Engineering, or a related field
• 3+ years of hands-on, proven experience in DFT implementation and verification (Scan, MBIST, LBIST, JTAG)
• Deep familiarity or mastery of our industry-leading ecosystem: TestMAX, VCS, Fusion Compiler (FC), PrimeTim, and Verdi
• Familiarity with 3rd party tools such as Siemens Tessent, Cadence Xcellium
• Exceptional communication skills in both Vietnamese and English

Benefits:

• Work with the best engineers around the world
• Continuous learning with unlimited access to Synopsys training
• Inclusive culture workspace where every background is celebrated, valued, and empowered to do its best work
• Competitive rewards: highly competitive salary, robust health benefits, and performance bonuses