Senior Mask Layout Design Engineer

NVIDIA is seeking a Senior Mask Layout Design Engineer to join a dynamic team responsible for handling high-speed mixed-signal circuit designs.

You will perform physical layout for mixed-signal functions like PLLs, high-speed SerDes, and Analog to Digital converters in sub-micron CMOS technologies using Cadence tools.

Responsibilities:

• Perform physical layout for mixed-signal functions
• Work with ASIC and mixed-signal engineers to customize designs for integration in VLSI products
• Take part in floor planning, custom layout, and verifying against design rules and schematics

Requirements:

• BSEE or equivalent experience
• Minimum of 5+ years validated experience in Mask and Layout Design
• Deep understanding of analog circuit layout concepts in submicron CMOS technologies
• Expertise with Cadence custom circuit design tools, particularly Virtuoso
• Experience with verification tools such as Dracula, Hercules, Calibre, and Primeyield
• Proficiency in scripting languages like Perl, Python, Skill, etc.
• Knowledge of DRC and LVS checking flows, ability to customize decks