Layout Design, Staff Engineer

Overview

You will work as a Layout Design, Staff Engineer at Synopsys, a leading provider of engineering solutions from silicon to systems. You will be responsible for designing and developing cutting-edge semiconductor solutions, focusing on intricate tasks such as chip architecture, circuit design, and verification.

Job Description

You have spent years in the trenches of custom layout, working on designs where a 10-micron mistake costs months and where matching, symmetry, and parasitic control are not nice-to-haves but the entire point. You know that a great floorplan is not about fitting everything in, it is about making the right tradeoffs between area, routing congestion, and signal integrity before anyone writes a single polygon.

At Synopsys, you will work on DDR and HBM PHY IP that powers the memory subsystems in everything from data centers to AI accelerators. The work is hard, the standards are high, and the team expects you to bring both hands and brain.

Responsibilities

• Lead layout development for next-generation DDR and HBM PHY IP across 7nm, 5nm, and below in FinFET and GAA process technologies
• Own floorplanning, layout execution, and design reviews for critical analog and mixed-signal blocks within memory PHY subsystems
• Drive layout quality through PERC, EMIR, DFM checks, LEF generation, and release readiness, ensuring designs meet foundry and customer specifications
• Collaborate with circuit design, verification, and product engineering teams to resolve layout-related issues, optimize for area and performance, and meet project schedules
• Mentor junior layout engineers on matching techniques, ESD and latch-up strategies, IO frame requirements, and deep submicron layout best practices
• Estimate effort, plan schedules, and execute layout deliverables in cross-functional project settings with accountability for timelines and quality
• Support customer-specific PHY requirements including bond-pad layout, pitch constraints, and custom IO configurations

The Impact You Will Have

• Enable Synopsys customers to integrate high-performance, low-power memory subsystems into SoCs powering AI, 5G, automotive, and cloud applications
• Accelerate time-to-market for next-generation DDR and HBM IP by delivering layout that works the first time and scales across process nodes
• Raise the technical bar for the layout team through hands-on mentorship, design reviews, and shared best practices that improve quality and efficiency
• Reduce design respins and foundry-related issues by catching deep submicron effects, parasitic mismatches, and DFM violations early in the layout cycle
• Strengthen cross-functional collaboration between layout, circuit design, and product teams, ensuring alignment on requirements, schedules, and tradeoffs
• Build reusable layout methodologies and IP blocks that scale across future memory PHY products and process technologies
• Contribute to Synopsys Silicon IP's reputation for delivering world-class, production-proven memory interface solutions

Requirements

• Bachelor's or Master's degree in Electronics Engineering, VLSI Design, or related field
• 5+ years of hands-on custom layout experience, with demonstrated leadership on complex analog or mixed-signal IP projects
• Deep expertise in layout for 7nm and below process nodes, including FinFET and GAA technologies, with strong understanding of deep submicron effects
• Proficiency in layout matching techniques, ESD and latch-up design, PERC, EMIR analysis, DFM checks, and LEF generation
• Experience with PHY-level IP development, including bond-pad layout, IO frame design, and customer pitch requirements
• Proven ability to lead projects, estimate effort, plan schedules, and deliver high-quality layout on time in cross-functional settings
• Experience with DDR, HBM, or high-speed memory interface IP is a strong plus

Benefits

• Comprehensive medical and healthcare plans
• Time away programs
• Family support
• ESPP
• Retirement plans
• Competitive salaries