Design-for-Test (DFT) Engineer — ASIC Backend

We are seeking multiple Design-for-Test (DFT) Engineers , ASIC Backend to join our Boeing Electronic Products team in El Segundo or Huntington Beach, CA. The DFT team drives architecture, verification, and post-silicon validation for leading-edge ASICs.

Key Responsibilities:

• Design and implement DFT architectures: TAP/JTAG, IJTAG (IEEE 1687), Boundary Scan (BSCAN), MBIST, and scan compression
• Develop and validate TAP/JTAG and IJTAG infrastructures, BSDL/ICL/PDL artifacts, and ATPG pattern generation
• Drive pattern generation, coverage optimization, memory test validation, and silicon debug (scan, at-speed, bring-up)
• Integrate DFT features across the chip design flow and collaborate with cross-functional teams to ensure robust DFT integration
• Coordinate with external partners/customers on custom DFT interfaces and security requirements when applicable
• Contribute to development and deployment of DFT methodologies for next-generation products
• Occasional travel and after-hours meetings during critical milestones

Basic Qualifications:

• Bachelor of Science degree in Engineering (with a focus in Electrical, Mechanical or Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry or non-US equivalent qualifications directly related to the work statement
• 2+ years of experience in Design for Testability (DFT) or equivalent
• Strong knowledge of ASIC/logic design flow, HDL (Verilog/SystemVerilog), static timing analysis, and ECO processes
• Hands-on expertise with TAP/JTAG, IJTAG (IEEE 1687), Boundary Scan (IEEE 1149.1), MBIST, scan compression, ATPG, at-speed test, and silicon debug
• Proficiency in scripting (Tcl/Perl/Python) and DFT verification methodologies
• Excellent analytical, problem-solving, and communication skills

Preferred Qualifications:

• 5+ years of related engineering experience (Experienced, Level 3)
• 9+ years of related engineering experience (Lead, Level 4)
• Active U.S. Secret Security Clearance
• Requirements development and traceability experience
• FPGA implementation including constraints and timing closure
• Static timing analysis experience
• Understanding of timing fundamentals and CDC concepts
• Verification collaboration experience
• High-speed interfaces, processor integration, memory subsystems, or SoC integration
• Mentoring or technical leadership exposure
• Familiarity with industry-standard tools and methodologies

Benefits:

• Competitive base pay and variable compensation opportunities
• Health insurance, flexible spending accounts, health savings accounts, retirement savings plans, life and disability insurance programs
• Paid and unpaid time away from work

Salary Range:

• Associate (Level 2): $98,600 - $133,400
• Experienced (Level 3): $119,850 - $162,150
• Lead (Level 4): $146,200 - $197,800