ASIC Physical Design Engineer — Synthesis and Timing

We are seeking an ASIC Physical Design Engineer , Synthesis and Timing to join our Boeing Electronic Products team in El Segundo, CA. You will play a crucial role in implementing advanced SoCs used in mission-critical satellite and space applications. Your responsibilities will include:

• Driving frontend and backend implementation, including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and ECO implementation
• Ensuring clean netlist handoffs and predictable convergence by partnering with RTL, verification, DFT, and backend partner companies
• Supporting chip-level integration, top-level timing closure, signoff readiness, and tapeout activities
• Contributing to methodology, automation, tool evaluations, and flow documentation
• Troubleshooting complex cross-domain timing issues and proposing robust, repeatable fixes

As a Boeing engineer, you'll join a diverse, collaborative team solving high-impact challenges in complex semiconductor design. We offer a competitive salary, with ranges of $98,600 - $133,400 for Associate (Level 2) and $119,850 - $162,150 for Experienced (Level 3).

Requirements:

• Bachelor of Science degree in Engineering (Electrical, Mechanical, or Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry, or non-US equivalent qualifications
• 1+ years of practical experience in synthesis and static timing analysis (STA)
• Solid understanding of timing convergence, constraints generation/management, and logic synthesis at block or full-chip level
• Familiarity with DFT, UPF/CPF power intent, ECO implementation, and signoff flows
• Experience with industry-standard EDA tools for synthesis, STA, and equivalence checking
• Proficiency in scripting (Tcl, Python, Perl) for flow automation and analysis
• Strong analytical, problem-solving, and communication skills

Preferred Qualifications:

• 5+ years of related engineering experience
• Active U.S. Secret Security Clearance
• Experience with large, timing-challenging ASIC blocks and cross-domain timing convergence
• Hands-on experience across the complete physical design flow (synthesis, floorplanning, P&R, CTS, STA, physical verification)
• Background in radiation-hardened or space-qualified ASIC design

Benefits:

• Competitive base pay and variable compensation opportunities
• Health insurance, flexible spending accounts, health savings accounts, retirement savings plans, life and disability insurance programs, and paid time away from work