ASIC Physical Design Engineer

Join the Cisco Silicon One team in Bangalore, India, and participate in designing and verifying leading-edge multimillion gate ASICs used in Cisco's core products.

As a Physical Design Engineer, you will work on creating next-generation state-of-the-art networking chips in advanced process nodes.

Key responsibilities:

• Drive the backend process through the entire RTL2GDS Implementation flow
• Focus on performance and die size optimization
• Work with hierarchical floor planning, place and route, timing closure, power integrity, static timing verification, physical verification, and equivalence checks

Requirements:

• Eligibility: 2027 graduates only
• Strong grasp of digital design, CMOS technology, VLSI principles, timing, and power fundamentals
• Experience in establishing and sustaining strong relationships with the extended team
• Excellent communication skills (verbal and written)
• Solid scripting skills for automating workflows

What You'll Bring:

• Ability to manage multiple tasks and work toward long-term goals
• Solid understanding of engineering fundamentals, digital design fundamentals, and technical problem-solving skills
• Experience in navigating the complete RTL to GDSII flow
• Understanding of key metrics like setup and hold timing, clock skew, congestion, IR drop, electromigration, DRC, LVS, PVT corners, and SDC constraints

Why Cisco?

• Revolutionizing how data and infrastructure connect and protect organizations in the AI era
• 40 years of innovation to create solutions that power human-technology collaboration
• Worldwide network of experts and opportunities for growth

Disclaimer:

• Cisco follows a strict hiring process; beware of fraudulent recruiters
• Any communication from Cisco will be through official channels, with interviews and screening