Analog Design, Staff Engineer

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

You have spent years working at the boundary between analog design and customer-facing deliverables, and you know that a model is only as good as the confidence it gives the engineer using it.

You are comfortable moving between SPICE simulations, characterization data, and behavioral model extraction without losing sight of what the customer needs to close timing on their board.

High-speed interfaces like DDR5, LPDDR5, HBM3, and UCIe do not intimidate you. You understand their signaling protocols, their edge cases, and what makes a timing model trustworthy at 6400 MT/s. At Synopsys, you will build the timing and IBIS models that memory controllers and PHY customers depend on to bring up their systems.

Responsibilities

• Generate and validate IBIS models for DDRn, LPDDRn, HBM, and UCIe memory interface IP products, ensuring compliance with industry standards
• Develop timing characterization data and customer-facing timing collateral for board-level design and signal integrity analysis
• Extract behavioral models from transistor-level simulations and correlate them against silicon characterization results across PVT corners
• Work with analog design teams to capture circuit behavior and ensure models reflect real silicon performance
• Debug model discrepancies, timing violations, and signal integrity issues reported by customers or internal validation teams

The Impact You Will Have

• Enable customers to successfully integrate Synopsys memory interface IP into their SoCs with accurate, reliable timing and IBIS models
• Reduce customer support escalations and silicon respins by catching model inaccuracies before tape-out
• Accelerate time-to-market for advanced memory products by streamlining the characterization and model release process
• Improve model quality and consistency across DDR, LPDDR, HBM, and UCIe product families through rigorous validation
• Support signal integrity closure for high-speed memory interfaces operating at multi-gigabit data rates in AI and data center applications

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or related field
• 5+ years of hands-on experience in analog/mixed-signal design, characterization, or modeling for high-speed interfaces
• Strong understanding of IBIS modeling standards and timing model formats used in memory interface design
• Direct experience with DDR, LPDDR, HBM, or other high-speed memory interface protocols and signaling
• Proficiency with SPICE simulation tools such as HSPICE or Spectre for transistor-level characterization and model extraction
• Experience with scripting languages like Python, Perl, or Tcl for automation is a strong plus

Who You Are

• You can look at a timing violation or an IBIS model mismatch and quickly narrow down whether it is a corner case issue, an extraction problem, or a real circuit behavior
• You communicate model assumptions and limitations clearly to both design teams and customers without burying important details in jargon
• You work well with cross-functional teams including circuit designers, layout engineers, and applications engineers who depend on your models
• You take ownership of your deliverables from initial extraction to final customer release

Benefits

• Comprehensive medical and healthcare plans that work for you and your family
• In addition to company holidays, we have ETO and FTO Programs
• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
• Purchase Synopsys common stock at a 15% discount, with a 24-month look-back
• Save for your future with our retirement plans that vary by region and country
• Competitive salaries