Analog Design, Sr Architect

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

You are a Principal-level analog design leader with deep expertise in high-speed SerDes and silicon-proven analog macros. You operate at the architecture and system boundary, translating standards and product requirements into robust, scalable circuit and layout implementations. You lead through technical influence by setting direction, driving alignment across teams, and mentoring engineers to deliver high-quality outcomes. You are recognized for sound judgment in power, area, and performance trade-offs, disciplined verification methodology, and the ability to resolve complex cross-domain issues spanning analog, digital calibration and control, and physical design.

Responsibilities

• Own macro-level architecture, design, and implementation of critical analog circuits for SerDes IP across TX, RX, and clock paths.
• Interpret SerDes standards and system architecture to define detailed analog specifications, budgets, and design targets including jitter, noise, linearity, settling, latency, power, and area.
• Drive top-level architecture trade-offs and define scalable circuit platforms reusable across product variants and process nodes.
• Lead and track technical execution across multiple sub-block owners, identify risk early, remove blockers, and ensure alignment to schedule and product goals.
• Define clear interfaces between analog macros and digital calibration, adaptation, and control, partnering with RTL and firmware teams to co-define algorithms and observability hooks.
• Define and enforce robust verification strategies using advanced SPICE and simulator capabilities including corner and Monte Carlo analysis, aging, mismatch, noise, transient jitter, PVT sweeps, and reliability checks.
• Champion best practices in modeling including Verilog-A behavioral models to accelerate system validation and improve correlation between block and top-level results.
• Drive silicon correlation plans by defining key measurements, mapping results to simulations, and feeding learnings back into design improvements.
• Provide technical oversight to physical layout to minimize parasitics, coupling, device stress, and process variation sensitivity, ensuring reliability and ESD are addressed from the start.
• Guide FinFET layout strategies for mismatch, symmetry, routing, shielding, EM and IR, and high-speed interconnect integrity.
• Present architecture rationale, simulation results, and risk assessments in peer and customer reviews, responding to technical questions with data-backed clarity.
• Consult on electrical characterization and test strategy for SerDes IP macros, influencing DFT and bring-up hooks and lab debug workflows.
• Mentor junior and mid-level engineers, setting a high technical bar for design quality, documentation, and review rigor.
• Contribute to team capability through reusable collateral, methodology improvements, and onboarding practices as the organization scales.

The Impact You Will Have

• Set technical direction for key SerDes analog macros, enabling best-in-class performance and reliability for next-generation standards.
• Improve predictability and quality through stronger verification methodology, correlation strategy, and design reuse.
• Elevate cross-functional execution across analog, layout, and digital teams, reducing integration risk and accelerating tapeout readiness.
• Provide technical leadership in customer engagements, strengthening Synopsys’ reputation for silicon-proven IP.
• Develop engineering talent through mentorship and technical leadership, strengthening long-term organizational capability.

Requirements

• PhD with 10+ years, or MSc with 12+ years of SerDes or high-speed analog design experience with multiple silicon successes.
• Demonstrated ability to lead macro-level architecture and deliver complex analog IP through tapeout and silicon validation.
• Deep transistor-level design expertise and strong CMOS and FinFET fundamentals.
• Silicon-proven experience implementing circuits for TX, RX, and clock paths within SerDes architectures.
• In-depth knowledge of SerDes sub-circuits such as equalizers, samplers, drivers, serializers, deserializers, VCOs, phase interpolators, DLLs, PLLs, bandgap references, ADCs, and DACs.
• Advanced skills guiding FinFET CMOS layouts to minimize parasitics and local device mismatches.
• Awareness of ESD and reliability issues including circuit techniques and layout strategies.
• Proficiency with EDA tools for schematic entry, physical layout, and design verification.
• Experience with SPICE simulators for detailed circuit analysis.
• Familiarity with analog behavioral modeling and simulation control using Verilog-A.
• Programming experience in TCL, Perl, C, Python, and MATLAB for design automation and data analysis.
• Clear potential to lead a team in the near future as the team continues to grow.

Benefits

• Comprehensive medical and healthcare plans that work for you and your family.
• In addition to company holidays, we have ETO and FTO Programs.
• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
• Purchase Synopsys common stock at a 15% discount, with a 24-month look-back.
• Save for your future with our retirement plans that vary by region and country.
• Competitive salaries.