Physical Design Engineer, Synthesis and Implementation

NVIDIA is seeking a Physical Design Engineer with expertise in Synthesis to join its Networking Silicon engineering team. The successful candidate will develop high-speed communication devices, delivering high throughput and low latency.

Job Overview: As a Physical Design Engineer, you will own RTL-to-gate synthesis and QoR convergence for complex digital blocks and hierarchical partitions. You will optimize synthesis strategies, constraints, and flows to meet performance, power, and area targets. Additionally, you will analyze design bottlenecks and QoR regressions, collaborating with various teams to resolve them.

Key Responsibilities:

• Own RTL-to-gate synthesis and QoR convergence for complex digital blocks and hierarchical partitions.
• Optimize synthesis strategies, constraints, and flows to meet performance, power, and area targets.
• Analyze design bottlenecks and QoR regressions, collaborating with RTL, timing, architecture, and physical design teams to resolve them.
• Support physical implementation from floorplanning and power planning through routing and timing closure.
• Automate design setup, execution, reporting, and issue triage while improving project-wide methodologies and best known methods.

Requirements:

• BSEE, MSEE, or equivalent experience.
• 2+ years of experience in synthesis and physical implementation on advanced process nodes.
• Strong proficiency with Synopsys Fusion Compiler, Cadence Genus, or comparable synthesis tools.
• Hands-on experience with synthesis constraints, timing analysis, QoR optimization, and the full place-and-route flow.
• Strong analytical and debugging skills across RTL, synthesis, timing, and physical implementation.
• Proficiency in Python, Perl, Tcl, and Make.
• Strong communication and multi-functional collaboration skills.

Benefits: You will also be eligible for equity and benefits.