Description
NVIDIA is seeking design engineers to join a team working on industry-leading GPUs and SOCs. The role involves physical verification for full-chip integration and tapeout on the latest process nodes.
Responsibilities:
- Own physical verification for the full chip, taking designs from block-level assembly through full-chip integration and tapeout on the latest process nodes like TSMC A16 and TSMC 3nm.
- Own full-chip physical verification signoff , DRC, LVS, antenna , across block, partition, and top levels, and drive convergence to a clean tapeout database.
- Push the frontier of 3D die stacking and heterogeneous integration , verifying die-to-die interfaces and stitching together dies built on entirely different process nodes into a single working system.
- Be at the leading edge of Angstrom class technology, enabling signoff for breakthroughs like Super Power Rail backside power delivery and nanosheet GAA transistors.
- Reinvent how signoff is done with AI , building ML- and LLM-powered automation for root-cause analysis, and flow optimization.
- Partner with the methodology and CAD/technology groups to define and deploy correct-by-construction flows that catch issues early and reduce signoff iterations.
- Cross-functional collaboration with P&R, Timing, IR, Library team to drive design closure on time.
Requirements:
- BE/BTECH/MTECH, or equivalent, with 5+ years of experience in Physical Design Verification, full chip integration and tapeouts on the latest technology nodes.
- Strong understanding of Physical Implementation and VLSI design concepts.
- Expertise in signoff tools like Calibre, ICV, EDI, FC.
- Good understanding of the RTL2GDSII concepts related to synthesis, place & route, CTS, timing convergence, layout closure.
- Good problem-solving skills.