Description
We are now looking for a highly motivated DFT Engineer to join this multifaceted and innovative hardware team at NVIDIA. Our Design-for-Test Engineering team works on crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most sophisticated semiconductor chips.
In this highly technical role, you will work on end-to-end DFT for the most sophisticated chips in the world, from methodology, to deployment to post-silicon lifecycle support. You will partner with top EDA tool vendors to develop new capabilities to support NVIDIA requirements, and with internal CAD to drive efficiency via automations. You will work with NVIDIA VLSI and Operations teams to deliver the scan feature in all product segments at NVIDIA. You will help mentor junior engineers on test designs and trade-offs including cost and quality.
To succeed in this role, you will need to pursue a BSEE or MSEE (or equivalent experience). You will need knowledge in defining scan test plans, BIST including memories and IOs, fault modeling, ATPG and fault simulation. You will need excellent analytical skills in verification and validation of test patterns and logic on sophisticated and multi-million gate designs using vendor tools. You will need good exposure to multiple domains including RTL & clocks design, STA, place-n-route and power, to ensure you are making the right trade-offs. You will need experience in Silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing, and test program development.
Preferred qualifications include strong programming and scripting skills in Perl, Python or Tcl.