Senior Signal and Power Integrity Engineer

We are looking for a Senior Signal and Power Integrity Engineer to join our team. As a Senior Signal and Power Integrity Engineer, you will be responsible for crafting creative Signal and Power Integrity solutions to complex system design problems.

Responsibilities:

• Work on system-level power integrity simulations of NVlinks 200Gbs+, PCIe, and other HSIO such as DP2.1/HDMI2.1/CSI/USB4.
• Design and optimize Power Delivery Network (PDN) across interposers, packages, and PCBs.
• Perform SI channel analysis for spec development: DP2.1/HDMI FRL2.
• Improve SI/PI models through lab measurements.
• Automate simulation, gather data, analyze, and visualize using JMP, MATLAB or similar tools.
• Work in a dynamic cross-functional role to optimize package, PCB, ASIC, mixed signal circuit.
• Extract post-layout SI/PI models for project review sign-off.

Requirements:

• BS/MS-Electrical Engineering or equivalent experience.
• 5+ years of industry experience.
• Strong understanding of electromagnetics including transmission line theory and via properties, and the SI/PI/EMI applications.
• Hands-on use of 3/2.5-D modeling tools like ANSYS HFSS/Q3D/SIwave, Cadence PowerSI.
• Experience with PDN evaluation using layout extraction tools for packages and PCBs and spice-based time domain simulations for power noise.
• Experience with die power delivery modeling – mixed-signal blocks & digital and associated tools like CSM/Redhawk, Raptor-X.
• Familiarity with voltage regulator modeling for board power supplies using simplis or spice.
• Familiarity with use of VNA, TDR, DSO.
• Familiarity with transient simulation in tools and understanding of eye diagram methodology.
• Measurement and simulation correlation experience.

Preferred Qualifications:

• Experience with Matlab, Python, VBS, or C for simulation automation.
• Exposure to interface timing budgets and system modeling.
• SI analysis flow including frequency and time domain simulation.
• PDN analysis flow including model generation and time domain simulation.
• PSIJ Analyses involving co-simulation of circuits and PDN models.
• Familiarity with high-speed I/O design concepts including clock generation, transmitter & receiver design, and equalization schemes.
• Develop novel algorithms & new methodologies to improve SI/PI/EMI modeling efforts.