Description
We are looking for an experienced Engineer who will lead the development of rapid IC packaging of individual die, to enable Failure Analysis and NPI tasks ahead of high-volume manufacturing.
This will include planning & driving related R&D with multiple internal and external partners and you will be responsible for establishing advanced packaging processes needed to meet our NPI goals regarding packaging turn-around-time, reliability, and chip-package interaction.
Prior knowledge of Package related Failure Analysis is beneficial.
Responsibilities
- Package Development & Prototyping: Drive the process, mechanical, thermal, and material evaluation of the latest IC packages. Manage rapid prototyping builds, package stack-ups, and assembly processes to bring new packaging architectures from concept to small volume for FA and NPI use cases.
- Material Characterization: Pioneer new packaging & die-level processing methodologies and evaluate innovative packaging materials (e.g., molding compounds, substrates, adhesives).
- Failure Analysis & Debug: Coordinate comprehensive physical and electrical failure analysis on prototype builds, reliability-tested components to determine root causes of failures.
- Multi-functional Collaboration: You’ll be embedded into the IC Failure Analysis team and collaborate with IC & Package design teams, process & product engineering. Collaborate with foundries and OSAT (Outsourced Semiconductor Assembly and Test) partners to develop & test the required processes, tooling, and workflows.
Requirements
- B.S., M.S., or Ph.D., or equivalent experience in Materials Science, Mechanical Engineering, Electrical Engineering, Physics, or a related semiconductor field.
- Packaging Expertise: Deep understanding of flip-chip, 2.5D/3D packaging, wire bonding, and advanced substrate architectures.
- Experience: 12+ years of hands-on experience in IC packaging development and/or package design, NPI (New Product Introduction).
- Design & Simulation Tools: Familiarity with IC package EDA software (e.g., Cadence Allegro Package Designer) and Finite Element Modeling (FEM) tools like ANSYS or ABAQUS is a strong plus.
- FA Tooling Proficiency: At a minimum, you’ll need basic understanding of advanced packaging related FA techniques and equipment, such as SEM, EDX, CSAM, X-Ray, and LIT.
You will also be eligible for equity and benefits.
This listing is enriched and indexed by YubHub. To apply, use the employer's original posting:
https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-IC-Packaging-Development-Engineer_JR2020052