Description
Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.
You have spent a decade or more designing digital logic that has to hold up in real silicon, not just pass simulation, and you know that the difference between a block that tapes out clean and one that comes back with a respin is usually a micro-architecture decision made six months earlier. High-speed communication protocols are your territory. You have worked on DDR, HBM, or similar interfaces enough times to know where the edge cases live and how to design around them without overbuilding.
What You'll Be Doing
- Define micro-architecture for mixed-signal IP blocks from industry specifications and internal architecture definitions, balancing performance, power, area, latency and timing for HPC applications
- Develop RTL for complex digital blocks within high-speed communication IP, including DDR and HBM interfaces
- Model circuit behavior for analog and mixed-signal components to enable co-design and early validation
- Define and refine synthesis constraints, working closely with physical design and timing closure teams to ensure your blocks meet targets
- Run and review code quality checks (Lint, CDC and RDC analysis), catching issues early in the development cycle
- Evaluate design trade-offs across multiple dimensions and recommend solutions that align with product goals and market requirements
- Mentor engineers on your team, reviewing designs, providing technical guidance, and helping them build the judgment that comes with experience
The Impact You Will Have
- Your micro-architecture decisions will define the performance and efficiency profile of next-generation memory IP used in high-performance computing systems
- The RTL you develop will be synthesized, verified, and manufactured in leading-edge process nodes, directly affecting product competitiveness
- Your behavioral models will enable early co-design between digital and analog teams, reducing integration risk and schedule slip
- The constraints and design practices you establish will set the quality bar for the broader IP development team
- Your mentorship will accelerate the growth of engineers around you, building the technical depth the team needs to scale
- The trade-off analysis you provide will inform product roadmap decisions and help leadership prioritize the right features for the right markets
- Your attention to CDC, RDC, and code quality will reduce downstream debug time and improve first-pass silicon success rates
What You'll Need
- Master's degree in Electrical Engineering, Computer Engineering, or a related field
- 10+ years of hands-on ASIC digital design experience, with a strong track record of blocks that have taped out and worked
- Deep expertise in high-speed communication protocols, specifically DDR, HBM, or similar memory interfaces
- Solid understanding of low power design techniques and how to apply them in performance-critical contexts
- Strong knowledge of clock domain crossing (CDC) and reset domain crossing (RDC) analysis, and experience resolving violations in complex designs
- Experience with synthesis flows, including physical-aware synthesis and constraint definition for timing closure
- Familiarity with mixed-signal design environments and the ability to work effectively with circuit designers and behavioral models is a strong plus
Benefits
- Comprehensive medical and healthcare plans that work for you and your family
- In addition to company holidays, we have ETO and FTO Programs
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
- Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
- Save for your future with our retirement plans that vary by region and country
- Competitive salaries