Description
As a Senior Analog Layout Engineer on the Silicon One Optics team, you will architect the physical blueprint for the world's fastest optical interconnects. You will own block-to-top integration for next-gen 100G, 200G, and 400G per lambda architectures, pushing silicon past standard limits.
Responsibilities:
- Power Next-Gen Optics: Directly build and optimize complex analog and mixed-signal layouts for groundbreaking 100G–400G/lambda optical solutions.
- Own the Silicon Lifecycle: Drive full-flow execution from concept and floorplanning through post-layout extraction, sign-off, tapeout, and post-silicon bring-up.
- Solve High-Speed Challenges: Master complex parasitic, signal integrity, and thermal tradeoffs alongside world-class circuit design, packaging, and CAD teams.
- Set the Standard: Shape design methodologies, mentor rising engineering talent, and raise the bar for physical execution across the group.
Minimum Qualifications:
- Bachelors + 7 years of related experience, or Masters + 4 years of related experience, or PhD + 1 year of related experience
- Prior experience supporting block-level layout efforts through tapeout
- Prior experience in physical verification and custom layout design, specifically with custom analog layout experience in FINFET 7nm, 5nm, or 3nm
- Prior experience with Cadence Virtuoso or similar custom layout tools
Preferred Qualifications:
- Analog & Custom Layout Design: Prior experience in device-level layout techniques (matching, symmetry, shielding, common-centroid, interdigitation, guard rings, isolation structures) and critical design concepts including parasitic control, thermal management, and signal integrity. Custom analog experience in TSMC 2nm or below is a plus.
- EDA Tools & Signoff Flows: Prior experience with EDA tools like Cadence Virtuoso and Calibre (or equivalent) in a Linux environment, with a strong command of physical signoff flows including DRC, LVS, ERC, parasitic extraction, and EM/IR analysis.
- Tapeout & Automation: Prior experience with ASIC/SoC tapeout processes and scripting capabilities (Python, Perl, or TCL) for layout automation.
- Collaboration: Prior experience working with cross-functional teams across multi-location teams.
Benefits:
- Medical, dental and vision insurance
- 401(k) plan with a Cisco matching contribution
- Paid parental leave
- Short and long-term disability coverage
- Basic life insurance
- Paid time away (10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees, 1 paid day off for employee's birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness)
- Optional 10 paid days per full calendar year to volunteer