Senior Engineering Leader - ATE Development Strategy

NVIDIA is seeking a senior engineering leader to define and scale its ATE development strategy for complex silicon products from new product introduction through high-volume manufacturing.

This role leads a global organization responsible for production test architecture, hardware and program development, silicon correlation, quality screening, yield enablement, cost-of-test optimization, and test automation.

The ideal candidate brings deep semiconductor test expertise, strong interpersonal leadership, and can drive execution across developing, product engineering, manufacturing, reliability, and supplier ecosystems.

Responsibilities:

• Set the vision, roadmap, and operating model guiding ATE creation throughout new product introductions and sustaining production.
• Lead and develop a distributed team composed of managers and senior engineers covering test hardware, program development, characterization, correlation, productization, and data-driven test optimization.
• Drive production test readiness for complex devices, including test coverage, guardband strategy, yield learning, defect screening, quality containment, and test cost reduction.
• Establish scalable methodologies, standards, release criteria, and quality gates for ATE development and deployment.
• Partner closely with architecture, circuit build, test integration, product engineering, system test, reliability, silicon operations, manufacturing, and collaborators outside the company to ensure strong design-to-test alignment.
• Lead the strategy for ATE platform selection, vendor engagement, capacity readiness, and capital planning needed to support product ramps.
• Use data and analytics to improve silicon correlation, test limits, binning strategies, excursion response, and long-term product quality.
• Build a high-performance leadership culture through strong hiring, interpersonal development, succession planning, and multi-functional influence.

Requirements:

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related field, or equivalent experience.
• 18+ years of relevant semiconductor experience, including 8+ years of management experience. Leading managers and distributed engineering organizations.
• Deep expertise in ATE development for high-volume silicon, SoC, ASIC, or GPU-class products.
• Shown success leading organizations through NPI, silicon bring-up, characterization, production ramp, yield improvement, and quality execution.
• Strong understanding of ATE platforms, test hardware design, test program development, instrumentation, silicon correlation, statistical analysis, and production test methodologies.
• Consistent track record to partner across design, DFT, product engineering, failure analysis, reliability, manufacturing, and supplier or OSAT ecosystems.
• Experience owning roadmaps, budgets, staffing plans, and operational priorities for large-scale engineering organizations.
• Strong executive communication skills with the ability to influence senior collaborators and drive alignment across technical and business teams.

Preferred Qualifications:

• Experience with GPU, AI, networking, or other high-performance compute products.
• Track record of reducing test cost while improving outgoing quality and production scalability.
• Strong background in test automation, data infrastructure, and improvement guided by data insights.
• Experience building and scaling global test-development organizations across multiple sites and external partners.
• Familiarity with system-level test, product binning, performance and power optimization, or silicon operations workflows.

The base salary range is 320,000 USD - 483,000 USD. You will also be eligible for equity and benefits.