Description
Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.
You are a seasoned digital design professional with a passion for architecting and implementing state-of-the-art ASIC solutions. Bringing over a decade of hands-on experience in RTL design, you thrive in complex, multi-site environments and are driven by the challenge of building high-performance IP Cores for consumer and automotive applications. Your expertise spans industry protocols such as UCIe, Ethernet, PCIe, DDR, MPHY,UFS,UNIPRO and more, making you a go-to technical leader for die-to-die communication solutions.
Responsibilities:
- Architecting and implementing high-performance RTL designs for advanced IP cores, focusing on die-to-die communication protocols such as UCIe for consumer and automotive applications.
- Creating comprehensive architecture and micro-architecture documents, translating functional specifications into detailed design solutions for complex components.
- Leading and executing design tasks including RTL coding, synthesis, CDC analysis, debugging, and test development, ensuring robust and reliable ASIC designs.
- Collaborating closely with the verification team to plan, execute, and close verification cycles, achieving high coverage and design quality.
- Interacting with customers to clarify specification requirements and ensure design alignment with end-user needs.
- Mentoring and technically leading a team of designers, fostering skill development and knowledge sharing within a global, multi-site environment.
Requirements:
- BSEE or MSEE in Electrical Engineering, with 12+ years of relevant industry experience in ASIC digital design.
- Proficiency in one or more protocols: Ethernet, DDR, Die-to-Die Communication, PCIe, CXL, USB,MPHY,UFS,UNIPRO etc.
- Expertise in micro-architecture, RTL coding (Verilog/SystemVerilog), and design flows for ASIC implementation.
- Hands-on experience with synthesis, CDC analysis, formal checking, and static timing analysis.
- Familiarity with high-speed design, P&R-aware synthesis, and advanced tools such as Fusion Compiler.
- Experience with revision control systems (e.g., Perforce) and scripting languages like Perl/Shell.
- Exposure to quality processes in IP design and verification.
- Demonstrated ability to technically lead and mentor a team of designers.
Benefits:
- Comprehensive medical and healthcare plans that work for you and your family.
- In addition to company holidays, we have ETO and FTO Programs.
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
- Purchase Synopsys common stock at a 15% discount, with a 24-month look-back.
- Save for your future with our retirement plans that vary by region and country.
- Competitive salaries.