Description
Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.
You have spent years in the trenches of physical design, working on silicon that actually tapes out and ships in products people use. You know that the difference between a PHY that meets timing and one that doesn't often comes down to decisions made during floorplanning, and you are the kind of engineer who sees those decisions coming. You have worked with ICC2 and FC long enough to know their quirks, their strengths, and when to push back on a flow that isn't going to scale. FinFet brought new challenges, and you learned to navigate them not by reading whitepapers but by closing designs under real constraints.
Responsibilities
- Implement DDR and HBM PHYs for customer ASICs and SOCs, taking designs from RTL through physical implementation, timing closure, and signoff
- Run synthesis, place and route, and physical verification using ICC2, Fusion Compiler, and ICV on advanced FinFet nodes
- Perform design for test insertion and ATPG, ensuring manufacturable and testable designs
- Serve as the technical lead on design engagements, coordinating with internal Synopsys teams and external customer design teams to deliver on schedule
- Provide regular project updates to management and front customer-facing communication on technical progress, risks, and mitigation plans
- Debug complex timing, power, and physical design issues across multi-million gate designs, often under tight tapeout schedules
- Guide junior engineers on physical design methodology, tool usage, and best practices for closure on advanced nodes
The Impact You Will Have
- Deliver DDR and HBM PHY IP that meets performance, power, and area targets for customer chips shipping in high-volume production
- Reduce project risk by catching design issues early and proposing solutions that keep schedules on track
- Strengthen customer relationships through reliable execution and clear technical communication during critical project phases
- Improve internal design flows and methodologies by contributing lessons learned from real tapeouts back into the team's knowledge base
- Accelerate the growth of junior engineers by providing hands-on mentorship on complex physical design challenges
- Expand Synopsys' reputation as a trusted partner for memory subsystem design services in the semiconductor industry
- Enable faster time-to-market for customer products by delivering high-quality, first-pass-correct PHY implementations
Requirements
- 5+ years of hands-on experience in ASIC physical design, with multiple successful tapeouts on advanced nodes
- Deep working knowledge of Synopsys tools including Design Compiler, PrimeTime, ICC2 or Fusion Compiler, and ICV
- Experience implementing designs on FinFet process technologies (7nm, 5nm, or below)
- Proven ability to close timing, power, and signal integrity on complex, high-speed interface designs
- Strong debugging skills across the physical design flow, from synthesis through signoff
- Experience with DDR or HBM PHY design is a strong plus
- Familiarity with design for test methodologies and ATPG tools is a plus