Senior Silicon Product Engineer – Manufacturing

NVIDIA's Silicon Co-Design Group is seeking a Senior Silicon Product Engineer – Manufacturing to join the Testability, Manufacturability, Reliability & Quality (TMRQ) team.

The successful candidate will co-design and implement SLT Production diagnostics for silicon features in a high-volume manufacturing environment, verify POR specifications, and support post-silicon validation for complex semiconductor chips.

Responsibilities:

• Partner with multi-functional HW/SW teams to determine test coverage and constraints for high-volume manufacturing screens
• Collaborate with SW and platform teams to support and improve SLT testing infrastructure, debug knobs, and data collection features
• Co-design SLT testability scope and coverage enhancements for Nvidia's manufacturing testing
• Prototype and fine-tune speed, power, circuits, yield, and quality for effective silicon coverage in the SLT socketed environment
• Co-design, develop, and maintain SLT testing flows and incorporate takeaways from silicon and correlate to design
• Define procedures to facilitate Silicon correlation activities between production testing infrastructure and internal Si characterization and diagnostics programs
• Support customer-facing and quality teams during customer escalations
• Drive alignment for manufacturability, test time optimization and reduction, cost vs. coverage tradeoffs, etc.
• Initiate and drive process improvements and preventative actions through root cause analysis and data analytics

Requirements:

• Bachelor's or Master's Degree or equivalent in Microelectronics/Electrical/Electronic/Computer Engineering or equivalent experience
• 8+ years of relevant proven experience in silicon Post-silicon PVT validation and/or High-volume manufacturing testing for sophisticated SoCs, GPUs, CPUs, or similar
• Hands-on lab experience with silicon bring-up, lab debug, test content bring-up, and correlation to Si characterization, yield, and coverage optimization
• Strong EE fundamentals, device physics, knowledgeable in Silicon design, statistics, STA concepts, signal integrity, fault analysis, sampling, and computer architecture
• Excellent interpersonal skills and demonstrated ability to drive multi-functional alignment around plans, dependencies, and sign-off criteria
• Prior ownership of manufacturing test strategy for a major silicon product (e.g., GPU/SoC/CPU) from early planning through ramp to QS/production
• Strong data analysis skills. Prior experience working with volume data is a plus
• Good understanding of firmware/driver structures and their interaction with HW
• Problem-solving, debugging, analysis, and logical reasoning skills with examples to prove it
• Experience with Python, BASH, Linux, and scripting

Benefits:

• Base salary range: 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5
• Equity and benefits package