Description
We are seeking a Senior Mask Layout Design Engineer to join our dynamic team. As a Senior Mask Layout Design Engineer, you will be responsible for performing physical layout for mixed-signal functions like PLL's, high-speed I/O circuits, general I/O's, and ESD structures designs in innovative sub-micron CMOS technologies using Cadence tools.
You will work with ASIC and mixed-signal engineers to customize designs for integration in VLSI products. Your job duties will include floor planning, custom layout, and verifying against design rules and schematics.
To be successful in this role, you should have:
- A BSEE or equivalent experience. An MSEE is a plus.
- 8+ years of relevant mask design/layout experience.
- Tape-out experience with FinFET technology is required. Experience with TSMC N5/N4/N3 is preferred.
- Experience with high-speed SerDes/RF layout design is helpful, and experience with top-level integration would be excellent to have.
- Deep understanding of analog circuit layout concepts in submicron CMOS technologies.
- Validated experience with Cadence custom circuit design tools, particularly Virtuoso.
- Experience running and debugging DRC and LVS with verification tools such as ICV/Calibre.
- Ability to work optimally in a team, good interpersonal skills, and positive energy.
- Proficiency in scripting languages like Perl, Python, Skill, etc. is a plus.
- Knowledge of DRC and LVS checking flows, ability to customize DRC and LVS decks.
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is $132,000 - $207,000 for Level 4, and $148,000 - $235,750 for Level 5. You will also be eligible for equity and benefits.